All of the vendors are still using power-of-two MLC (i.e. 4 or 8 levels) right? I wonder when we'll start seeing 3 level (1.58 bits/cell) or 5 level (2.32 bits

All of the vendors are still using power-of-two MLC (i.e. 4 or 8 levels) right? I wonder when we'll start seeing 3 level (1.58 bits/cell) or 5 level (2.32 bits/cell) MLC start appearing? It's more complex to visualize, but the controller already abstracts the details of the storage quite a bit so it's not hard to imagine it spreading your 512 bytes across 2585 instead of 2048 cells. Some implementations are already doing compression so you could even have the algorithm's output be a tristate stream instead of a binary one if that's marginally more efficient for the silicon. Another thing I wonder is how much neighboring cells interfere with each other. If that's the case, the most efficient data packing might even rely on bit encodings for multi-cell groups that avoid the combinations that are most likely to cause interference (similar to the 64b/66b encoding in gigabit ethernet, for example) Again, the controller has to do this type of thing already to implement ECC so it seems like a straightforward extension. Note that I'm not saying that either of these techniques avoid the "dead end" you're talking about -- they're both just ways of squeezing a tiny bit more out of the density/reliability curve at the margins. I'm just imagining how complicated flash controllers might get as they try to capture the last bits of life in the technology.