3 ms·
I wonder if you can boot it without populating any DRAM sockets.
by hedora 2y ago
I wonder if you can boot it without populating any DRAM sockets.
- dmitrygr 2y agoThat would require either rewriting drivers to never use DMA or making sure that all DMA controllers are able to write into and read from L3 directly.
- bee_rider 2y agoI would be pretty curious about such a system. Or, maybe more practically, it might be interesting to have a system pretends the L3 cache is ram, and the ram is the hard drive (in particular, ram could disguise itself as the swap partition, to so the OS would treat is as basically a chunk of ram that it would rather not use).
- compressedgas 2y agoPhilip Machanick's RAMpage! (ca. 2000) > The RAMpage memory hierarchy is an alternative to a conventional cache-based hierarchy, in which the lowest-level cache is managed as a paged memory, and DRAM becomes a paging device.
- afr0ck 2y agoSo, essentially, you're just doing cache eviction in software. That's obviously a lot of overhead, but at least it gives you eviction control. However, there is very little to do when it comes to cache eviction. The algorithms are all well known and there is little innovation in that space. So baking that into the hardware is always better, for now.
- edward28 2y agoIntel has such a CPU with the previous gen called the xeon AMX with up to 64gb of HBM on chip. It could use it a cache or just memory.
- lewurm 2y agoFirmware is using cache as RAM (e.g. https://www.coreboot.org/images/6/6c/LBCar.pdf https://www.coreboot.org/images/6/6c/LBCar.pdf) to do early init, like DRAM training. I guess later things in the boot chain rely on DRAM being set up probably though.