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The weirdest one of the bunch is the AMD EPYC 9175F: 16 cores with 512MB of L3 cache! Presumably this is for customers trying to minimize software costs that ar
by smolder 2y ago
The weirdest one of the bunch is the AMD EPYC 9175F: 16 cores with 512MB of L3 cache! Presumably this is for customers trying to minimize software costs that are based on "per-core" licensing. It really doesn't make much sense to have so few cores at such an expense, otherwise. Does Oracle still use this style of licensing? If so, they need to knock it off.
The only other thing I can think of is some purpose like HFT may need to fit a whole algorithm in L3 for absolute minimum latency, and maybe they want only the best core in each chiplet? It's probably about software licenses, though.
- aecmadden 2y agoThis optimises for a key vmware license mechanism "Per core licensing with a minimum of 16 cores licensed per CPU.".
- puzzlingcaptcha 2y agoWindows server licensing starts at 16 cores
- londons_explore 2y agoPlenty of applications are single threaded and it's cheaper to spend thousands on a super fast CPU to run it as fast as possible than spend tens of thousands on a programmer to rewrite the code to be more parallel. And like you say, plenty of times it is infeasible to rewrite the code because its third party code for which you don't have the source or the rights.
- RHab 2y agoAbaqus for example is by core, I am severly limited, for me this makes totally sense.
- bob1029 2y agoAnother good example is any kind of discrete event simulation. Things like spiking neural networks are inherently single threaded if you are simulating them accurately (I.e., serialized through the pending spike queue). Being able to keep all the state in local cache and picking the fastest core to do the job is the best possible arrangement. The ability to run 16 in parallel simply reduces the search space by the same factor. Worrying about inter CCD latency isn't a thing for these kinds of problems. The amount of bandwidth between cores is minimal, even if we were doing something like a genetic algorithm with periodic crossover between physical cores.
- Jestzer 2y agoMATLAB Parallel Server also does per-core licensing. https://www.mathworks.com/products/matlab-parallel-server/license-model.html#:~:text=MATLAB%2520Parallel%2520Server%E2%84%A2%2520is,checked%2520out%2520from%2520the%2520license https://www.mathworks.com/products/matlab-parallel-server/li....
- forinti 2y agoYou can pin which cores you will use and so stay within your contract with Oracle.
- heraldgeezer 2y agoWindows server and MSSQL is per core now. A lot of enterprise software is. They are switching to core because before they had it based on CPU sockets. Not just Oracle.
- bee_rider 2y ago512 MB of cache, wow. A couple years ago I noticed that some Xeons I was using had a much cache as the ram in the systems I had growing up (millennial, so, we’re not talking about ancient commodores or whatever; real usable computers that could play Quake and everything). But 512MB? That’s roomy. Could Puppy Linux just be held entirely in L3 cache?
- hedora 2y agoI wonder if you can boot it without populating any DRAM sockets.
- dmitrygr 2y agoThat would require either rewriting drivers to never use DMA or making sure that all DMA controllers are able to write into and read from L3 directly.
- bee_rider 2y agoI would be pretty curious about such a system. Or, maybe more practically, it might be interesting to have a system pretends the L3 cache is ram, and the ram is the hard drive (in particular, ram could disguise itself as the swap partition, to so the OS would treat is as basically a chunk of ram that it would rather not use).
- compressedgas 2y agoPhilip Machanick's RAMpage! (ca. 2000) > The RAMpage memory hierarchy is an alternative to a conventional cache-based hierarchy, in which the lowest-level cache is managed as a paged memory, and DRAM becomes a paging device.
- afr0ck 2y agoSo, essentially, you're just doing cache eviction in software. That's obviously a lot of overhead, but at least it gives you eviction control. However, there is very little to do when it comes to cache eviction. The algorithms are all well known and there is little innovation in that space. So baking that into the hardware is always better, for now.
- Aurornis 2y agoMany algorithms are limited by memory bandwidth. On my 16-core workstation I’ve run several workloads that have peak performance with less than 16 threads. It’s common practice to test algorithms with different numbers of threads and then use the optimal number of threads. For memory-intensive algorithms the peak performance frequently comes in at a relatively small number of cores.
- CraigJPerry 2y agoIs this because of NUMA or is it L2 cache or something entirely different? I worked on high perf around 10 years ago and at that point I would pin the OS and interrupt handling to a specific core so I’d always lose one core. Testing led me to disable hyperthreading in our particular use case, so that was “cores” (really threads) halfed. A colleague had a nifty trick built on top of solarflare zero copy but at that time it required fairly intrusive kernel changes, which never totally sat well with me, but again I’d lose a 2nd core to some bookkeeping code that orchestrated that. I’d then tasksel the app to the other cores. NUMA was a thing by then so it really wasn’t straightforward to eek maximum performance. It became somewhat of a competition to see who could get highest throughout but usually those configurations were unusable due to unacceptable p99 latencies.
- afr0ck 2y agoNUMA gives you more bandwidth at the expense of higher latency (if not managed properly).
- yusyusyus 2y agonew vmware licensing is per-core.
- elil17 2y agoMany computational fluid dynamics programs have per core licensing and also benefit from large amounts of cache.