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The coreboot docs claim that modern AMD parts no longer support cache-as-RAM. https://doc.coreboot.org/soc/amd/family17h.html https://doc.coreboot.org/soc/amd/
by bpye 2y ago
The coreboot docs claim that modern AMD parts no longer support cache-as-RAM.
https://doc.coreboot.org/soc/amd/family17h.html https://doc.coreboot.org/soc/amd/family17h.html
- SV_BubbleTime 2y agoLame. Using it as TCM ram seems super useful. Although you would need to fight/request it from the OS, so technically I see why they might ditch it.
- hales 2y agoWow, thanks for the link, I had no idea: > AMD has ported early AGESA features to the PSP, which now discovers, enables and trains DRAM. Unlike any other x86 device in coreboot, a Picasso system has DRAM online prior to the first instruction fetch. Perhaps they saw badly trained RAM as a security flaw? Or maybe doing it with the coprocessor helped them distribute the training code more easily (I heard a rumour once that RAM training algos are heavily patented? Might have imagined it).