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Does anyone know if modern AMD chips allow mapping the L3 cache and using it as TCM instead of cache? I know older non-X86 processors supported this (and often
by addaon 2y ago
Does anyone know if modern AMD chips allow mapping the L3 cache and using it as TCM instead of cache? I know older non-X86 processors supported this (and often booted into that mode so that the memory controllers could be brought up), but not sure if it's possible today. If so, that would sure make for some interesting embedded use cases for a large DRAM-less system...
- bpye 2y agoThe coreboot docs claim that modern AMD parts no longer support cache-as-RAM. https://doc.coreboot.org/soc/amd/family17h.html https://doc.coreboot.org/soc/amd/family17h.html
- SV_BubbleTime 2y agoLame. Using it as TCM ram seems super useful. Although you would need to fight/request it from the OS, so technically I see why they might ditch it.
- hales 2y agoWow, thanks for the link, I had no idea: > AMD has ported early AGESA features to the PSP, which now discovers, enables and trains DRAM. Unlike any other x86 device in coreboot, a Picasso system has DRAM online prior to the first instruction fetch. Perhaps they saw badly trained RAM as a security flaw? Or maybe doing it with the coprocessor helped them distribute the training code more easily (I heard a rumour once that RAM training algos are heavily patented? Might have imagined it).
- londons_explore 2y agoIf you keep your working set small enough, you should be able to tell the CPU it has RAM attached, but never actually attach any RAM. It would never flush any cache lines to RAM, and never do any reads from RAM.
- to11mtm 2y agoPart of me is asking whether some of the 'mitigations' to various things in microcode have necessitated reads from RAM?