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There is something about RISC-V that really inspires lots of hackers and it’s not really technical thing AFAICT.
by Pet_Ant 2y ago
There is something about RISC-V that really inspires lots of hackers and it’s not really technical thing AFAICT.
- bee_rider 2y agoIt is cool as heck that truly open hardware might actually win in our lifetimes. (ARM was an interesting start, but too much licensing).
- chrisjj 2y ago> There is something about RISC-V that really inspires lots of hackers "Not Arm" :)
- trq01758 2y agoSimplicity, it's a modern MOS 6502. Base RISC-V has even less instructions than 6502.
- Joker_vD 2y agoAlso it has less registers (32 vs. 256 in the zero page) and less addressing modes.
- wk_end 2y agoBut the 6502's "registers" are much smaller and you can do much less with them. You can't really sensibly compare the two approaches so superficially.
- crackez 2y agoYet the same number of register bytes (when only counting 6502's zero page)... 32x8 = 256 bytes...
- brucehoult 2y ago31x4 = 124 bytes :-) The Zero register doesn't have to physically exist, and we're talking about 32 bit CPUs e.g. Pi Pico 2 here, right. Ok, 128 bytes if you add in the PC. Except for RV32E -- as seen in the very popular $0.10 CH32V003 -- which has 15x4 = 60 bytes of GPRs, plus the PC. Plus usually a few CSRs on practical CPUs, though Zicsr is an extension so you don't have to have it.
- snvzz 2y agoCan they really be called registers, when they're bytes in DRAM? It really is just a convenient short addressing mode. The 6502 has actual registers, A/X/Y and the specialized S/P/PC.
- brucehoult 2y ago> Can they really be called registers, when they're bytes in DRAM? Yes they can, because that's just an implementation detail. Registers are nothing more than a conveniently short address for frequently-accessed working storage. Sometimes they are in their own address space (which in modern use usually doesn't have indirect/computed addressing, but can), but sometimes they are in the same address space as RAM e.g. in AVR the first 32 bytes of RAM are the registers (which might or might not be implemented in the same technology). Some early / small AVRs didn't have any other RAM. The same is true of PIC and 8051. And then there is the TMS9900 where the only on-chip registers were the PC and a pointer to where in RAM the working registers were stored. It seems entirely appropriate to refer to the 6502's Zero Page as "registers" given that 1) it barely has any others, and 2) the very fundamental for modern software base+offset addressing mode exists only using two zero page bytes as the base. You would otherwise be reduced to using self-modifying code for any access via pointer. If the 6502 ISA had not become obsolete for other reasons -- the desire for more than 8 bit ALUs and 16 bit addresses -- it is entirely likely that as CPUs became faster than RAM and more transistors were able to be put in the CPU then future 6502s would have brought Zero Page on-chip.
- acegopher 2y agoThe same could be said of the ARM Cortex-M0+.
- kragen 2y agoThe Cortex-M0's Thumb-1 is a really unpleasant instruction set compared to ARM, Thumb-2, RISC-V, or ARM64.
- brucehoult 2y agoThough no worse than 16 or 32 bit x86 (without FPU), and probably better because the lower 8 registers are general-purpose. Also you can get something useful from the "spare" five registers r8-r12 as they support MOV, ADD and CMP with any other register, plus BX. Sadly you're on your own with PUSH/POP except for PUSH LR / POP PC. Thumb-1 (or ARMv6-M) is fairly similar to RISC-V C extension. It's overall a bit more powerful because it has more opcodes available and because RVC dedicates some opcodes to floating point. RVC only lets you do MV and ADD on all 32 (or 16 in RV32) registers, not CMP (not that RISC-V has CMP anyway). Plus, RVC lets you load/store any register into the stack frame. Thumb-1 r8-r14 need to be copied to/from r0-r7 to load or store them. But on the other hand, RVC is never present without the full-size 4 byte instructions, even on the $0.10 CH32V003, making that a bit more pleasant than the similar price Cortex M0 Puya PY32F002.
- jecel 2y agoIt is better to say RVC is almost never present without the full-size 4 byte instructions since we have one counter example: https://github.com/gsmecher/minimax https://github.com/gsmecher/minimax This is an experimental rather than practical design that only directly implements the compressed instructions in hardware and then implements the normal RV32I instructions in "microcode" written using the compressed instructions.
- kragen 2y agoMinimax is a super cool design! I think it's not really a counterexample, because it does implement the uncompressed instructions, just more slowly.
- marssaxman 2y agoFor me, it's the fact that it is a truly open standard, with no licensing entanglements. It has the potential to be a durable ecosystem, worth investing in.
- KerrAvon 2y agoIt's a bunch of things; many of the reasons are actually technical. It's very simple to compile to RISC-V instructions.
- zyffsht 2y agoTyyygyg
- brucehoult 2y agoThe offsets for J{AL} and Bcc are a little tricky, though only half a dozen lines of code to sort out.
- rootnod3 2y agoFor me, part of it is also the beauty of the ISA. I think it is just really well thought out with its extensions and namespacing for custom ISAs.