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An overview of the new EPYC Turin server processors is here: https://www.phoronix.com/review/amd-epyc-9005 https://www.phoronix.com/review/amd-epyc-9005

• jsheard 2y ago
  The 9175F is kind of hilarious, it's just 16 cores but with 512MB of L3 cache between them. L3 cache is a per-chiplet resource so we can infer it has the same number of chiplets as the 128 core 512MB SKU, but 112 of the cores are disabled. Presumably that chip is aimed squarely at running software with per-core licensing as fast as possible with as few cores as possible.
  • crest 2y ago
    Is it confirmed that it doesn't just include lots of dummy silicon for mechanical support, at least 16 working cores and the I/O die?
    • jsheard 2y ago
      It's confirmed by the fact that it has 512MB of cache - reducing the number of functional chiplets would reduce the total amount of cache proportionately, so it has to be maxed out with the full set of chiplets. The other 16-core SKUs with just 64MB of cache are what you get when you reduce the number of chiplets and fill out the rest of the package with dummy silicon instead.