4 ms·

It's nice that they're finally starting to "compress" the instruction space. To take a related concept further, it would be nice if there were totally unportab

It's nice that they're finally starting to "compress" the instruction space. To take a related concept further, it would be nice if there were totally unportable, chip-superspecific ways of feeding uops directly, particularly with raw access to the unrenamed register file. Say you have an inner loop, and a chip is popular. Let your compiler take a swing at it. If it's way faster than the ISA translation, add a special case to the fat binary for a single function. Alas, it will probably never happen due to security, integrity, and testing costs.

larodi 2y ago
Is it only security which stands in the way of compilers devising their own instructions. Certain architectures potentially would allow this, and most of the chips, even MCUs as ESP32 (which run RISC-V-like LX7 cores), have microcode. It is apparent what the gains can be, what is the typical show stopper - security or proprietary microcode lang?
- worstspotgain 2y ago
  The uops aren't smart or terribly proprietary IIRC. Aside from security/integrity/testing, the documentation would have to be automated, and releasing it early might tip off competitors to some stuff. I don't think you'd even need to roll your own ISA, you'd just issue uops as a native ultra-low-level ISA. One issue (without further architectural help) is that you'd save and restore every register you touch, which is fine for an inner loop that's consequential enough. Another obstacle is any hardware that's shared among cores, such as memory coherency. In general, moving super-ad-hoc memory management into the compiler would suck for the compiler writers. Maybe some of your compiler can be a LLM? If performance is key, I would totally deploy this if I have faith in my tests - and maybe a way for the user to turn it off just in case.
  - larodi 2y ago
    Thanks, very informal. The part you save/restore every register you touch I don't quite ge. Is this a side effect of the uops execution or you meant something else? I like the idea LLM assistss in the process. not because llms can reason better than compiler, but because with this particular translation task, it should excel at. perhaps we gonna see some new compiler in 2025... there is some writing of it here https://arxiv.org/abs/2408.03408 https://arxiv.org/abs/2408.03408 and there is this https://medium.com/@zergtant/meta-releases-llm-compiler-a-compiler-based-on-large-language-models-with-both-compilation-and-cc3acfd2f7d6 https://medium.com/@zergtant/meta-releases-llm-compiler-a-co... both from 2024. Model is on HF.
p_l 2y ago
Some systems in the past exposed the ability to directly generate microprograms, but these days it does not really provide much benefit, especially given how different chips can be that you run on.

larodi 2y ago

Is it only security which stands in the way of compilers devising their own instructions. Certain architectures potentially would allow this, and most of the chips, even MCUs as ESP32 (which run RISC-V-like LX7 cores), have microcode. It is apparent what the gains can be, what is the typical show stopper - security or proprietary microcode lang?

worstspotgain 2y ago
The uops aren't smart or terribly proprietary IIRC. Aside from security/integrity/testing, the documentation would have to be automated, and releasing it early might tip off competitors to some stuff. I don't think you'd even need to roll your own ISA, you'd just issue uops as a native ultra-low-level ISA. One issue (without further architectural help) is that you'd save and restore every register you touch, which is fine for an inner loop that's consequential enough. Another obstacle is any hardware that's shared among cores, such as memory coherency. In general, moving super-ad-hoc memory management into the compiler would suck for the compiler writers. Maybe some of your compiler can be a LLM? If performance is key, I would totally deploy this if I have faith in my tests - and maybe a way for the user to turn it off just in case.
- larodi 2y ago
  Thanks, very informal. The part you save/restore every register you touch I don't quite ge. Is this a side effect of the uops execution or you meant something else? I like the idea LLM assistss in the process. not because llms can reason better than compiler, but because with this particular translation task, it should excel at. perhaps we gonna see some new compiler in 2025... there is some writing of it here https://arxiv.org/abs/2408.03408 https://arxiv.org/abs/2408.03408 and there is this https://medium.com/@zergtant/meta-releases-llm-compiler-a-compiler-based-on-large-language-models-with-both-compilation-and-cc3acfd2f7d6 https://medium.com/@zergtant/meta-releases-llm-compiler-a-co... both from 2024. Model is on HF.

p_l 2y ago

Some systems in the past exposed the ability to directly generate microprograms, but these days it does not really provide much benefit, especially given how different chips can be that you run on.