4 ms·

This is an instruction I would like to implement in RISC-V if it isn't already, (which yeah, I know, isn't very RISC like) movei (%r1),(%r2),(%r3),value Mo

This is an instruction I would like to implement in RISC-V if it isn't already, (which yeah, I know, isn't very RISC like) movei (%r1),(%r2),(%r3),value Move the contents of memory pointed to by r1, to the contents of memory pointed to by r2, applying the boolean operator <value>, with the memory pointed to by r3. Then increment all three registers by 4 to point to the next word. There was something similar to this in the Intel 82786 graphics chip which had a sort of minimal cpu part that could run simple "programs". And yeah, I really enjoyed the blitter on the Amiga. It was a really cool bit of hardware.

magicalhippo 2y ago
What's the value (no pun intended) of such an instruction if "value" is an immediate and not register-based? If it's an immediate then the compiler (human or machine) knows what the operation will be, so could just write that instead?
- ChuckMcM 2y ago
  The value is that a two instruction pipeline can do a blit at cache speed.
  - magicalhippo 2y ago
    I totally get why you'd want mem-to-mem instructions, it just seemed more interesting in a blitting context (and others) to have the operation not be static but rather register-based. But perhaps in practice it matters not, been a long time since I wrote blitting code. RISC-V already has what you want in terms of R-type instructions[1], ie "dest = src1 op src2" where "op" is effectively an immediate value, but being based on a load-store architecture it's only register-to-register of course. Though I suppose ISA-wise there's nothing in the way of making an extension that introduces "M-type instructions" which act like the R-type instructions but are mem-to-mem instead. How much that messes with everything else I have no idea. edit: ah, forgot about you wanting it to behave like movsb. Still, something that could be handled by the extension instruction. [1]: https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-1569c8d-2024-10-03/riscv-unprivileged.pdf https://github.com/riscv/riscv-isa-manual/releases/download/... (section 2.4.2)
  - Someone 2y ago
    But the “two instruction” part isn’t important there on most risc-v hardware, is it? That “memory to memory” instruction still routes the data through the CPU, so what does replacing a load instruction and a store instruction by a more complex but probably/likely slightly shorter load-store instruction bring if your CPU is much faster than your memory?
JonChesterfield 2y ago
Conditional move between registers is common. This is like masked load / stores with postincrement. Seems a reasonable instruction to me, if rather specialised.

magicalhippo 2y ago

What's the value (no pun intended) of such an instruction if "value" is an immediate and not register-based? If it's an immediate then the compiler (human or machine) knows what the operation will be, so could just write that instead?

ChuckMcM 2y ago
The value is that a two instruction pipeline can do a blit at cache speed.
- magicalhippo 2y ago
  I totally get why you'd want mem-to-mem instructions, it just seemed more interesting in a blitting context (and others) to have the operation not be static but rather register-based. But perhaps in practice it matters not, been a long time since I wrote blitting code. RISC-V already has what you want in terms of R-type instructions[1], ie "dest = src1 op src2" where "op" is effectively an immediate value, but being based on a load-store architecture it's only register-to-register of course. Though I suppose ISA-wise there's nothing in the way of making an extension that introduces "M-type instructions" which act like the R-type instructions but are mem-to-mem instead. How much that messes with everything else I have no idea. edit: ah, forgot about you wanting it to behave like movsb. Still, something that could be handled by the extension instruction. [1]: https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-1569c8d-2024-10-03/riscv-unprivileged.pdf https://github.com/riscv/riscv-isa-manual/releases/download/... (section 2.4.2)
- Someone 2y ago
  But the “two instruction” part isn’t important there on most risc-v hardware, is it? That “memory to memory” instruction still routes the data through the CPU, so what does replacing a load instruction and a store instruction by a more complex but probably/likely slightly shorter load-store instruction bring if your CPU is much faster than your memory?

JonChesterfield 2y ago

Conditional move between registers is common. This is like masked load / stores with postincrement. Seems a reasonable instruction to me, if rather specialised.