I've been in integrated circuit physical design for almost 30 years. What signal integrity issue are you referring to? For on chip nets we have SI issues from

I've been in integrated circuit physical design for almost 30 years. What signal integrity issue are you referring to? For on chip nets we have SI issues from cross coupling capacitance. For the last 25+ years the routers will try to move these nets apart and jump layers to avoid long cross coupled nets. The RC extraction tools have supported extraction of cross coupled nets and all of the delay calculators and static timing analysis tools to analyze victim / aggressor net coupling and filter out irrelevant nets if they don't switch in the same timing windows. Chiplets are combining multiple chips in the same package. I had a Pentium Pro from 1996 that did that. In the last 5 years chip packaging technology has continued to advance and we are stacking dies and more within the same package. SI between chips is not a new issue. There are tools to analyze that as well.