3 ms·
Intel (and almost everyone else tbh) didn’t fully appreciate how Denard scaling would play out at smaller nodes. They expected to keep lowering the transistor t
by throwup238 2y ago
Intel (and almost everyone else tbh) didn’t fully appreciate how Denard scaling would play out at smaller nodes. They expected to keep lowering the transistor threshold voltage alongside transistor size but that became increasingly difficult due to leakage currents.
- osnium123 2y agoThey also played with tricks like strained silicon on 90nm and high-k metal gate in 45 nm in order to boost performance and lower leakage respectively.