4 ms·
SRAM is scaling significantly more slowly than logic in recent process nodes.
by jrk 2y ago
SRAM is scaling significantly more slowly than logic in recent process nodes.
- ericd 2y agoAhh that explains it, thanks. Seems like a potentially large problem given their strategy.
- phonon 2y agoThey could use something like GCRAM[1] to double capacity if they had to...but it's not clear how much worse performance would be. [1]https://raaam-tech.com/products/ https://raaam-tech.com/products/
- nsteel 2y agoThe performance doesn't look great (yet). See Fig. 7 https://www.eng.biu.ac.il/fishale/files/2020/12/A-1-Mbit-Fully-Logic-Compatible-3T-Gain-Cell-Embedded-DRAM-in-16-nm-FinFET.pdf https://www.eng.biu.ac.il/fishale/files/2020/12/A-1-Mbit-Ful...
- phonon 2y agoCerebras runs at 1.1 GHz[1], and this was a much earlier design on 16nm so it might be a good fit by now. Their TSMC 5 nm version is scheduled for early 2025.[2] [1]https://cerebras.ai/blog/cerebras-architecture-deep-dive-first-look-inside-the-hw/sw-co-design-for-deep-learning https://cerebras.ai/blog/cerebras-architecture-deep-dive-fir... [2]https://www.eenewseurope.com/en/raaam-signs-lead-licensee-for-sram-replacement-technology/ https://www.eenewseurope.com/en/raaam-signs-lead-licensee-fo...
- nsteel 2y agoThey'd have to quadruple their performance to be relevant in the market generally, here's to hoping.
- phonon 2y agoYeah...but double density and 1/10 power consumption would be outstanding for ML type loads...hopefully they can get performance to at least the 1.x GHz range! I'm keeping an eye out...dollars to donuts Cerebras will be using this within a year, once it's qualified for TSMC 5nm.
- nsteel 2y agoNot so sure myself. eDRAM has been tried many times and yet here we all are, banging our heads against the SRAM scaling limits. It's such a huge risk for cerebras, they absolutely cannot afford to miss. But then you could say that about a wafer-scale chip...!