4 ms·
I’ve spent several evenings pondering the PIOs and whether I could adapt them to this project. I think there’s a reasonable chance that the answer is yes for th
by ckemere 2y ago
I’ve spent several evenings pondering the PIOs and whether I could adapt them to this project. I think there’s a reasonable chance that the answer is yes for the new RP2350. For the aforementioned 25 ksps per channel, I actually need something like a 25 MHz clock (64 channels at 16 bits). With the original 2040, I convinced myself it would be hard without overclocking. But with the new one quite possibly possible. Handling variable cable delays of 8-10 bits also requires buffering in a way that I couldn’t quite wrap my head around, but I bet someone could!
- bcrl 2y agoThat's 25 MHz if you're doing everything serially, but you could probably do it with a 11 or 12 bit parallel bus. There are ADCs on the market that have parallel rather than serial interfaces. The only reason I'm suggesting this is because 25ksps is a rate that's low enough that the headaches of using a parallel bus are minimal. Deskewing isn't all that hard to do, and there are plenty of designs you can steal ideas from. FPGAs generally have FIFOs in the SERDES that are used to deskew multilane protocols like PCIe or 40/100Gbps ethernet (in QSFPs). You bit/byte slip during training until things sync up, then throw an error and retrain if sync bits don't match what's expected (to keep the check in the fast path cheap). That should work in software as well, but it could very well be challenging at 25MHz. Those are but a couple of the reasons serializers / deserializers are giant complicated bits of intellectual property found on virtually every chip these days.