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Maximum performance is only one corner for optimization. We do not operate chips at high temperatures in our pocket; the goal is to get low power for the same f

Maximum performance is only one corner for optimization. We do not operate chips at high temperatures in our pocket; the goal is to get low power for the same functionality to have a long battery life, in which case parallelization means doubling the number of transistors while halving clock rates lowering the total power quadratically. It is also not more expensive per area to stack logic: by lowering the area of each die, you increase the yield of each in the stack.

d_tr 2y ago
You also save quite a bit of routing, right?
nabla9 2y ago
> by lowering the area of each die, you increase the yield of each in the stack. Nope. The yield is relative to the surface area in layers, not the die surface area.
- d_tr 2y ago
  You mean you have to stack the chips first to test them, in which case the whole stack would have to be discarded?
wtallis 2y ago
> We do not operate chips at high temperatures in our pocket; Sure we do. When you actually hit your phone's processor with a non-trivial workload, the die temperature very quickly spikes to near the safe limits for silicon (ie. 90+ °C). It's only if the workload is sustained for a relatively long time (eg. when gaming) that the heat starts to be conducted to the outside of the phone and drive further throttling of the processor to prevent those surfaces from reaching temperatures that aren't safe for human hands. Even when a phone is heat-soaked enough that it is enforcing skin temperature limits, there's still a much higher temperature at the die. > It is also not more expensive per area to stack logic: by lowering the area of each die, you increase the yield of each in the stack. The stacking process itself does not have perfect yield, even when assembling known-good dies. Every layer added increases the risk of the stack as a whole becoming non-functional. 3D stacked DRAM has mostly been limited to single-digit stack heights, despite being the easy case for die stacking: every die is the same, has a more or less identical workload (and thus similar thermal expansion) and uses the same interface with the same TSV locations. Most of that goes out the window if you're trying to make a large stack of various co-processors.

d_tr 2y ago

You also save quite a bit of routing, right?

nabla9 2y ago

> by lowering the area of each die, you increase the yield of each in the stack. Nope. The yield is relative to the surface area in layers, not the die surface area.

d_tr 2y ago
You mean you have to stack the chips first to test them, in which case the whole stack would have to be discarded?

wtallis 2y ago

> We do not operate chips at high temperatures in our pocket; Sure we do. When you actually hit your phone's processor with a non-trivial workload, the die temperature very quickly spikes to near the safe limits for silicon (ie. 90+ °C). It's only if the workload is sustained for a relatively long time (eg. when gaming) that the heat starts to be conducted to the outside of the phone and drive further throttling of the processor to prevent those surfaces from reaching temperatures that aren't safe for human hands. Even when a phone is heat-soaked enough that it is enforcing skin temperature limits, there's still a much higher temperature at the die. > It is also not more expensive per area to stack logic: by lowering the area of each die, you increase the yield of each in the stack. The stacking process itself does not have perfect yield, even when assembling known-good dies. Every layer added increases the risk of the stack as a whole becoming non-functional. 3D stacked DRAM has mostly been limited to single-digit stack heights, despite being the easy case for die stacking: every die is the same, has a more or less identical workload (and thus similar thermal expansion) and uses the same interface with the same TSV locations. Most of that goes out the window if you're trying to make a large stack of various co-processors.