3 ms·
With CMOS the heat puts hard limits for every type of stacking (transistor layers in a chip, or stacking CMOS chips). In DRAM tech you can stack several (4-8 a
by nabla9 2y ago
With CMOS the heat puts hard limits for every type of stacking (transistor layers in a chip, or stacking CMOS chips).
In DRAM tech you can stack several (4-8 at least) HMC memory layers on top of one logic layer.
SSD is moving from 100+ towards 1000 layer memory chips.
- apples_oranges 2y agoSSD layers: Do you mean each cell is storing around 100 different values or are cells layered on top of each other (each addressed separately etc.)?
- throwaway48476 2y agoThe cells are layered but each cell stores 4 bits in QLC.
- AnimalMuppet 2y agoQLC = "Quad Level Cell", if you're like me and didn't know that.
- d_tr 2y agoWhich is a strange name and underselling it btw, since there are 16 levels...
- gdiamos 2y agoIs this why there is more attention on PIM - processing in memory? You don’t burn active power?
- petra 2y agoIt's mainly as a way to overcome the bandwidth limits between memory and CPU. It will increase the heat density of the memory, but there's room to play there. Plus there are some designs that use analog electronics for compute, and it reduces power.
- CyberDildonics 2y agoPIM - processing in memory? I don't think this is something that actually exists in a working competitive state. I also don't think there is "more attention" by anyone actually working on cpus. You don’t burn active power? What does this mean?
- gdiamos 2y agoSSDs are 3D with high stacking. They retain data without burning power, unlike SRAM. What if you put some of these 3D transistors tightly integrated with a 3D SSD and power gated them? It seems like you would beat the memory wall. Obviously manufacturing that is beyond us today.
- CyberDildonics 2y agoIt seems like you would beat the memory wall. I don't know what this is supposed to mean. Why would putting coprocessing somewhere outside of the CPU be better than just sending data to storage?
- gdiamos 2y agoIt takes a lot of energy to move data
- 2y ago
- londons_explore 2y agoIf you know you are thermally limited, there are a bunch of designadjustments you can use to produce less heat. Lower clock speed, more regions powered off at any given time, clock gating, etc. By being able to stack logic, it will just change the way designs are made. for example, custom silicon to accelerate a specific operation, for example gzip compression, becomes far more attractive because now there is lots of 'spare' silicon area as long as it remains powered down 99% of the time.
- nabla9 2y agoSilicon area is expensive. And the logic becomes more expensive per area when you stack it. The whole purpose is to extract performance from the chip by making it dense and distances short.
- amirhirsch 2y agoMaximum performance is only one corner for optimization. We do not operate chips at high temperatures in our pocket; the goal is to get low power for the same functionality to have a long battery life, in which case parallelization means doubling the number of transistors while halving clock rates lowering the total power quadratically. It is also not more expensive per area to stack logic: by lowering the area of each die, you increase the yield of each in the stack.
- d_tr 2y agoYou also save quite a bit of routing, right?
- nabla9 2y ago> by lowering the area of each die, you increase the yield of each in the stack. Nope. The yield is relative to the surface area in layers, not the die surface area.
- d_tr 2y agoYou mean you have to stack the chips first to test them, in which case the whole stack would have to be discarded?
- giancarlostoro 2y ago> SSD is moving from 100+ towards 1000 layer memory chips. Does this increase capacity, performance or both? I'm by no means a hardware guru.
- mapt 2y agoThe upper limit of heat extraction is an interesting problem. Intel certainly seems to have bumped into a region with the i7-12900k and later where the chip is heat limited under all load tests even on watercooling, and improving significantly on the best air-coolers requires taking off the protective 'heatspreader' for closer contact with a heatpipe. Those heatpipes seem to be mostly watercooled. Some kind of supercritical CO2 heatspreader with direct die fluid contact perhaps?