6 ms·
Texas Instruments has FRAM in some of their microcontrollers. It's really pleasant to use. You write to it like any other part of RAM, the only difference being
by jonathrg 2y ago
Texas Instruments has FRAM in some of their microcontrollers. It's really pleasant to use. You write to it like any other part of RAM, the only difference being that the bytes stay where they are when you lose power. With something flash you need to be more careful with how you use it.
- technothrasher 2y agoI've been using it in a few projects at work as a replacement for flash backed serial RAM. It drops right in, as it is pin and function compatible with other small SPI and I2C nvram and eeprom chips, and isn't really much more expensive in small capacities.
- beeflet 2y agoWhat is the latency like vs DRAM?
- polpo 2y agoIn my experience with parallel FRAM, it’s as fast as SRAM and is a drop in replacement with the same timing. A lot of folks have replaced battery backed SRAM with FRAM on game consoles.
- beeflet 2y agoHoly cow thats cool. So It's like an expensive nonvolatile replacement for volatile memory. I wonder if in the future there could be computers with no sense of "memory vs storage", that it would all just be a single contiguous "memory". Instead of turning off the computer and hibernating, you just turn off the LCD backlight and the IO.
- grishka 2y agoYou would still need to turn the CPU off though. Or do you suggest replacing the registers and caches and all other volatile memory with this stuff?
- soganess 2y agoI'm not sure what the performance/persistence implications of this (FRAM) actually are... But to your point, simply copying the processor state to a known location in FRAM (0xFFFFFFF0) and having the start routine read state from that location seem like a very low overhead solution to the problem. How long would it really take to do something your computer does as part of preemptive multi-tasking? Nanoseconds? Milliseconds? We are talking about $order(hundred) of instructions
- gmueckl 2y agoThis may work on something with the complexity of a microcontroller or SoC, but becomes tricky beyond that. Any peripherals, especially removable ones would still need to be rediscovered and reinitialized on boot. Network connections may have died/reset while the system was off. Essentially, this scheme has all the major complications of resuming from sleep/hibernation in practice.
- mananaysiempre 2y agoBecause it is, for the most part, suspend to RAM aka S3.
- jasomill 2y agoWhile implemented virtually rather than physically, two well-known (and very different) examples of systems that unify memory and secondary storage under a single addressing scheme are Multics (1969) and the IBM System/38 (1978). Note that the present-day IBM i née AS/400 is a direct descendent of the System/38. References: https://en.wikipedia.org/wiki/Single-level_store https://en.wikipedia.org/wiki/Single-level_store https://dl.acm.org/doi/pdf/10.1145/363095.363139 https://dl.acm.org/doi/pdf/10.1145/363095.363139 http://bitsavers.org/pdf/ibm/system38/G580-0237-1_IBM_System_38_Technical_Developments_198007.pdf#page=65 http://bitsavers.org/pdf/ibm/system38/G580-0237-1_IBM_System... https://archive.org/details/insideas4000000solt/page/171/mode/1up https://archive.org/details/insideas4000000solt/page/171/mod...
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- saati 2y agoIt would burn out in a few hours.
- Retr0id 2y agoWhy? FRAM has extremely high write endurance.
- EGG_CREAM 2y agoI did notice from the article that reading is destructive, so every time you read (or at least every time you read a 0), you have to re-write it out. I wonder how much that affects the practical durability.
- nayuki 2y agoReading destroys the stored value; it doesn't necessarily destroy the physical material. Reading from memory is already destructive in DRAM (capacitor gets discharged), magnetic core memory (need to alter the magnetization state to read out how much energy was needed), and probably other technologies as well.
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- kens 2y agoYes, since reads destroy the data, each read causes a write. The chip will handle 100 trillion read/writes. So yes, the chip will wear out rapidly if you do a lot of reads.
- jonathrg 2y agoI can't really think of a use case where this could plausibly come up. It would take 3 years if you read the same memory location (uncached) 1 million times a second.
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- jonathrg 2y agoFor the specific chip I used (MSP430FR2355), you could read and execute code at max 8MHz without wait states. Which means it's reading at most 4MHz since each MSP430 instruction that accesses memory requires at least 2 cycles. So latency is at least 1/4MHz=0.25µs
- therein 2y agoI really like their FRAM products too. Ultra low power, high data endurance. They have this NFC FRAM MCU product that can be powered by the reader itself. I want someone to incorporate these into their hardware wallet products. Would also be very cool for high endurance data storage. I understand we are talking about kilobytes of storage but still they have very small packaging anyway, just use them (the SPI bus FRAM products) by the dozens.
- kjs3 2y agoYa...the TI MSP430 had (have) it. Nifty 16-bit arch (esp if you like PDP-11s) and FRAM was just as you say a joy to use versus Flash. Very low power as well.