And it always gets prematurely optimized to fit a specific problem instead of being made general purpose compute engine. FPGAs are essentially horrible systoli

And it always gets prematurely optimized to fit a specific problem instead of being made general purpose compute engine. FPGAs are essentially horrible systolic arrays. They're lumpy, and have weird routing hardware that isn't easy to abstract out. Those lead to multiple day compile times in some cases. They don't pipeline things by default. The programming languages used are nowhere near a good fit to the hardware. It's just a mess. It happens every time.