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ad RAM: the platform (if it is real) is little bit more interesting - they have cards with 16GB RAM per four 4-core CPUs (SoCs) - these cards are to be used tog

by mykhal 14y ago

ad RAM: the platform (if it is real) is little bit more interesting - they have cards with 16GB RAM per four 4-core CPUs (SoCs) - these cards are to be used together in amount of tens, connected with high speed switched fabric in the host board.. so it's something like server cluster on board design.. http://www.calxeda.com/technology/products/energycards/quadnode/ http://www.calxeda.com/technology/products/energycards/quadn...

reitzensteinm 14y ago
Now that's interesting. Why on earth aren't they leading with it? I can understand these kinds of faux benchmarks and whitepapers to convince pointy haired bosses to switch between mature, mainstream technologies. But the early adopters of fringe technology like this are going to be companies with specific needs, and those making the decisions are going to be highly technical. Not to generalize, but they (me included) love details and possibilities, and abhor marketing puffery. Calxeda should be sketching out novel ways to use the interconnect bandwidth to solve hard problems, with power efficiency x86 can't touch. Not running ab against an ARM core and misinterpreting the results. Sheesh.
- mykhal 14y ago
  well, there is a promising HP project Moonshot, which was going to build on this platform, but it seems that they recently decided to switch to Intel solution.. http://www.engadget.com/2012/06/20/project-moonshot-take-two-hps-low-power-gemini-servers-let-go/ http://www.engadget.com/2012/06/20/project-moonshot-take-two...
- brooksbp 14y ago
  Calxeda five XAUI (50 Gbps) to a 4 core 1.1GHz 5W. 200ns per hop. A ToR switch will slow you down to 2000-3500ns. Tilera TilePro64, 64 core 866MHz 22W, 1.7Tbps core-to-core, 46ns L1/L2 miss found in adjacent core, four XAUI (40 Gbps). When compared to Tilera, Calxeda has a high bandwith per compute ratio. But 200ns core-to-core is not as fast as 46ns. Tilera also has higher core/watt ratio.
zokier 14y ago
I think you misread that page. I think they mean that each SoC has one memory slot, which supports max 4GB RAM. So that 16 gigs is total amount for all the four CPUs. This still strongly points towards a 32-bit design.
- mykhal 14y ago
  16 GB per 4 CPUs does not mean 4GB per CPU? sorry for my english.. :)
  - hatcravat 14y ago
    16 GB shared among 4 CPUs is different from 4 CPUs which each access 4 GB of private memory.
    - unwind 14y ago
      The page says: Support for 16GB DDR3/3L memory via four (4) mini-DIMM sockets – one socket dedicated per SoC supports up to 4GB of ECC memory (supplied separately) Which really doesn't sound as if the memory is shared, to me.

by mykhal 14y ago

reitzensteinm 14y ago

Now that's interesting. Why on earth aren't they leading with it? I can understand these kinds of faux benchmarks and whitepapers to convince pointy haired bosses to switch between mature, mainstream technologies. But the early adopters of fringe technology like this are going to be companies with specific needs, and those making the decisions are going to be highly technical. Not to generalize, but they (me included) love details and possibilities, and abhor marketing puffery. Calxeda should be sketching out novel ways to use the interconnect bandwidth to solve hard problems, with power efficiency x86 can't touch. Not running ab against an ARM core and misinterpreting the results. Sheesh.

mykhal 14y ago
well, there is a promising HP project Moonshot, which was going to build on this platform, but it seems that they recently decided to switch to Intel solution.. http://www.engadget.com/2012/06/20/project-moonshot-take-two-hps-low-power-gemini-servers-let-go/ http://www.engadget.com/2012/06/20/project-moonshot-take-two...
brooksbp 14y ago
Calxeda five XAUI (50 Gbps) to a 4 core 1.1GHz 5W. 200ns per hop. A ToR switch will slow you down to 2000-3500ns. Tilera TilePro64, 64 core 866MHz 22W, 1.7Tbps core-to-core, 46ns L1/L2 miss found in adjacent core, four XAUI (40 Gbps). When compared to Tilera, Calxeda has a high bandwith per compute ratio. But 200ns core-to-core is not as fast as 46ns. Tilera also has higher core/watt ratio.

zokier 14y ago

I think you misread that page. I think they mean that each SoC has one memory slot, which supports max 4GB RAM. So that 16 gigs is total amount for all the four CPUs. This still strongly points towards a 32-bit design.

mykhal 14y ago
16 GB per 4 CPUs does not mean 4GB per CPU? sorry for my english.. :)
- hatcravat 14y ago
  16 GB shared among 4 CPUs is different from 4 CPUs which each access 4 GB of private memory.
  - unwind 14y ago
    The page says: Support for 16GB DDR3/3L memory via four (4) mini-DIMM sockets – one socket dedicated per SoC supports up to 4GB of ECC memory (supplied separately) Which really doesn't sound as if the memory is shared, to me.