4 ms·
If Apple’s going for one SME accelerator per base M4 chiplet, it’ll be interesting to see how to program scalably for Pro/Max/Ultra variants.
by nxobject 2y ago
If Apple’s going for one SME accelerator per base M4 chiplet, it’ll be interesting to see how to program scalably for Pro/Max/Ultra variants.
- wtallis 2y agoYou should be thinking in terms of CPU clusters, not chiplets. The Ultra is the only one with multiple chiplets, but all of their processors have multiple CPU clusters, and so far it's one AMX/SME per cluster.
- bee_rider 2y agoI guess the the CPU/cluster and cluster/chiplet ratios change from generation to generation?
- wtallis 2y agoThey're not constant even within a generation. The M3, M3 Pro, and M3 Max are each monolithic SoCs of different sizes (no chiplets) with different CPU cluster configurations, and the phone chip of the same generation is yet another configuration.
- astrange 2y agoThis isn't hard to deal with because it's just an evolution of having to check the # of CPU cores to know how many worker threads to start. But there are a few more problems because of cache hierarchies; touching the same memory from different CPU clusters at once can be extra slow, possibly even slower than fetching it from DRAM. This is called NUMA (which is ironic for a unified memory SoC.)
- jhugo 2y agoUnified but not uniform.
- nxobject 2y agoAh, thank you! That’s the right word. They’re on the same die, no, so “chiplet” isn’t the appropriate word?