5 ms·
Exploring the scalable matrix extension of the Apple M4 processor
- freeqaz 2y agoAny comparison with how much faster this is compared with the previous way of doing things on the CPU?
- svnt 2y agoBased on my understanding from the description, it is ~8x faster (250 GFLOPS) for vector ops (vs. SVE mode at 31 GFLOPS which is CPU-ish) and 60-100 times faster (e.g. 2005 GFLOPS) for matrix multiplication for single-precision values.
- jandrese 2y agoThat's alright, but not mindblowing. How does it compare to doing the same work on a GPU? Is there a particular set of tasks that GPUs struggle with that would be well suited for this? Or is this more a fig leaf over lousy GPU compute support in Apple land?
- bee_rider 2y agoApple should mostly care about power-efficient inference I think, right? Not training. Spinning up a GPU seems like something to avoid. I mean, I wonder how this thing compares to a gemm using all the cores in a cpu cluster. They might be ok with not even meeting that performance, if the accelerator can not hog all the cores and power. At least that’s what my uninformed gut says. The workload for these things is like: little AI enhancements inside conventional apps, I think.
- lxgr 2y ago> Spinning up a GPU seems like something to avoid. You can do inference on GPUs as well, and for anything other than very small/lightweight models, such as noise cancellation or maybe speech recognition, it's probably worth the initial overhead. I believe CoreML already splits workloads between CPU, NPU, and GPU as appropriate.
- jhugo 2y agoIt’s likely not worth the additional energy usage though, at least when running on battery.
- bee_rider 2y agoYeah, this is what I was getting at. In some sense, the list of “capabilities which don’t require spinning up the GPU” is expanded. Whether something could be done by spinning up the GPU is beside the point.
- huijzer 2y ago60 times faster could mean 2 minutes instead of 2 hours, or 2 seconds instead of 2 minutes. How is that not mind blowing, or at least very useful (for specific uses)?
- TinkersW 2y agoWhat? The article says this thing does 2005 GFOPs, aka 2 TFLOPS, which is decent, but we have had CPUs that could do more than this for a long time now. My Zen2 12 core does about 3 TFLOPs, and a modern 16 core Zen5 can do 8-10 TFLOPS(I'm unsure what clock speed it can maintain with all cores engaged). And that is generally purpose SIMD not specialized matrix stuff(less generally useful). Apple CPU's kinda suck at vector ops, but they aren't that bad, this thing is only mildly better. I would guess power savings is a big part of why they use this SVE streaming matrix mode.
- mmoskal 2y agoIIUC this the cpu in an iPad. The pro/max versions would be more appropriate to compare against the Zen when they are released.
- ein0p 2y agoI’m not sure why they added this feature. All Apple SoCs have far more energy efficient compute than the CPU. This would only make sense for really tiny models which need extremely quick forward pass. For such models the overhead of a GPU or Neural Engine kernel launch would be quite noticeable. But for those the old NEON was already OK, and if not, there also is a dedicated matrix unit there called AMX. Seems kinda random to me.
- adrian_b 2y agoThis replaces AMX, it is its successor. The older Apple CPUs implemented a custom form of AMX that was not standardized by Arm. Presumably as a result of cooperation with Apple, the Arm ISA now includes a set of instructions with the same purpose like the original Apple AMX. The newer Apple CPUs have been updated to use the standard Arm ISA, instead of their older proprietary ISA. In the Apple CPUs, the former AMX and the current SME provide a much higher throughput than the CPU cores, even if lower than the GPU, and a much lower latency than the GPU, even if higher than the CPU cores. AMX/SME is implemented as a separate accelerator, distinct from the CPU cores, because this saves power and area in comparison with implementing such instructions in each CPU core. The Apple CPUs do not attempt to compete in high-performance computing applications, so the extra throughput provided by a separate shared matrix operation accelerator is good enough for them.
- saagarjha 2y agoThis has both actually.
- adrian_b 2y agoThat must be for preserving the compatibility with the older software versions. The same happens in x86, where there are hundreds of obsolete instructions, which have been replaced by better instructions, but which are still supported to allow the execution of old programs. Both the new Arm SME instructions and the old Apple AMX instructions are executed by the same hardware matrix operation accelerator. Previously Arm has extended the Aarch64 ISA with the SVE instructions, in order to support the Fujitsu supercomputer. Then they were not satisfied with the original SVE and they have extended it into SVE2. I suppose that something similar has happened with SME. Apple must have negotiated with Arm the inclusion of matrix and vector operations implemented by a separate shared accelerator. The result was SME, which differs from the original AMX either because Apple has thought some improvements based on the experience with the first instruction set or because Arm has desired some changes from the Apple proposal.
- dividuum 2y ago> Although Apple has included a matrix accelerator in its devices since 2019, it used a proprietary instruction set inaccessible to developers, who officially could only use Apple-provided numerical libraries. How does that work? Does the hardware throw some kind of fault when using those instructions? Or are they merely undocumented and you could use them if you figure out how they work? I guess the second, as hinted by the "officially"?
- my123 2y agoMerely undocumented
- jonstewart 2y agoPeter Cawley has a good write-up on the undocumented M1/M2/M3 AMX instructions: https://github.com/corsix/amx https://github.com/corsix/amx
- bee_rider 2y agoAs others have said, just undocumented. IIRC there was a BLIS fork that used AMX instructions. I think it was unofficial though(?). It is hard to do science without properly documented tools.
- nxobject 2y agoIf Apple’s going for one SME accelerator per base M4 chiplet, it’ll be interesting to see how to program scalably for Pro/Max/Ultra variants.
- wtallis 2y agoYou should be thinking in terms of CPU clusters, not chiplets. The Ultra is the only one with multiple chiplets, but all of their processors have multiple CPU clusters, and so far it's one AMX/SME per cluster.
- bee_rider 2y agoI guess the the CPU/cluster and cluster/chiplet ratios change from generation to generation?
- wtallis 2y agoThey're not constant even within a generation. The M3, M3 Pro, and M3 Max are each monolithic SoCs of different sizes (no chiplets) with different CPU cluster configurations, and the phone chip of the same generation is yet another configuration.
- astrange 2y agoThis isn't hard to deal with because it's just an evolution of having to check the # of CPU cores to know how many worker threads to start. But there are a few more problems because of cache hierarchies; touching the same memory from different CPU clusters at once can be extra slow, possibly even slower than fetching it from DRAM. This is called NUMA (which is ironic for a unified memory SoC.)
- jhugo 2y agoUnified but not uniform.
- nxobject 2y ago
- softwaredoug 2y agoI just wish they’d make native tensorflow installation actually work without a million apple silicon specific exceptions :)
- TheFuzzball 2y agoThey will, just in time for everyone to have switched to pytorch!
- kjkjadksj 2y agoI wish they made computers that ran software like games again. Seems like the last few iterations they’ve been working hard on making computers that are able to run ai models a little faster. Are people really asking for that? I would think far more people would like to play a video game over rolling their own matrix multiplication, but I guess that’s why they pay the people at apple the big bucks because they must know best.
- jwells89 2y agoOverall, GPU strength is the best it's ever been in portable Apple devices by a significant margin. The problem isn't the hardware, it's that game developers are reticent to support anything that's not x86 Windows+DirectX or one of the consoles. It's often said that macOS/iOS supporting Vulkan would help and while I think that's true to an extent, native Vulkan support is still rare enough that it's not going to change all that much in terms of ease of porting. It might improve things on the front of running games through WINE (DirectX → Vulkan translation), but unless developers produce ARM builds of their games there's always going to be the overhead of being run through an x86 translator, which varies depending on how CPU heavy the game is.
- wkat4242 2y agoAnything other than metal will be a big win. It's just a non-starter for developers of desktop quality games. Mobile ports sure. But Apple has never really cared about gaming. During the powerpc era they had a short phase of paying aspyr to make some ports (most notably CoD 4 modern warfare and some battlefield ports) but it was over within a year. Then about a decade later they had a phase around the 320M chipset where they promoted game releases. And again within a year they dropped the efforts and also let their OpenGL go totally stagnant. This caused for example elite dangerous to drop support. Now we're stuck with metal. Apple is just too small in gaming for desktop game devs to bother with metal. Not sure if Vulkan will be best but metal surely isn't. And the added complexity of building for arm doesn't help either (arm on windows is non-existent on any hardware aimed at gaming) I don't think Apple and Mac gaming will ever really become serious. I'm sure that if they do partner with studios like the last few times they'll just abandon the efforts like they always have. I think the biggest problem is just Apple's total lack of interest (save for the few half-hearted efforts above) to make Mac gaming real.
- brcmthrowaway 2y agoI'm dim, whats the difference between SVE and SME?
- mrmuagi 2y agoVector vs Matrices. Higher dimensional.
- DanielLee5 2y agoGreat review.
- DanielLee5 2y ago[dead]
- rerdavies 2y agoIn my experience, based on profiling and optimizing of ML-based guitar amp models in the PiPedal project (https://rerdavies.github.io/pipedal/ https://rerdavies.github.io/pipedal/), when using only neon instructions, performance is almost completely constrained by L2 memory bandwidth. Compute cost almost completely disappear while waiting for memory loads and stores. So, although these devices have ferociously impressive FLOP rates, I'm extremely curious as to how the cost of memory loads and stores is going to work. I can very well imagine that having large local tile buffers is going to dramatically improve performance. But I'm curious how much. No matter how fast the compute speed is, it seems to me that performance of these sorts of devices in practice is going to be constrained by memory transfer rates. And perhaps by L1 caches in the tile compute unit that are better optimized for tile computation than the L1 cache on a general-purpose cPU. My current expectation: that performance of matrix multiplies increases linearly with respect to tile size. i.e. a tile size if 8x8 floats will perform twice as fast as a matrix multiplier with a tile size of 4x4, since doubling the tile size reduces the required transfers to and from L2 by a factor of two. So, compared to a basic A72 ARM neon (effectively, 4x8 tile size), I would expect about a 4x improvement by virtue of the fact that the tile size is larger on the Apple tile processor. Both entirely otherwise limited by the cost of L2 memory loads and stores. And maybe another 2x or 3x improvement because the tile processor L1 caches (tile buffers) are tuned for tile multiply/accumulate operations. Could somebody comment on how these devices actually perform on real matrix multiplies? It seems inconceivable to me that these devices will actually achieve peak FLOP rates in anything but meaningless test cases. And also somewhat of a meaningless exercise to measure peak performance using test cases that are designed to completely eliminate L2 memory transfers.