It is a proxy for performance in a sense. I think it's either logic density or some arbitrary weighting of PPA. It's definitely not the same as it was when we w

It is a proxy for performance in a sense. I think it's either logic density or some arbitrary weighting of PPA. It's definitely not the same as it was when we were scaling actual gate lengths. Although it seems the foundries are now making the minimum drawn length close to or the same as the process designation. This was less so the case in the 5-7nm generation. I wonder if people were being stupid about it...