Welp, this is going to be a miserable slog. I had the misfortune of writing a SystemVerilog parser once upon a time. The grammar is a huge and ambiguous muddle

Welp, this is going to be a miserable slog. I had the misfortune of writing a SystemVerilog parser once upon a time. The grammar is a huge and ambiguous muddle. SVA is a beast with no clear precedence on some of the operators. The standard's description of the preprocessor is an incoherent mess. Godspeed!