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Automated feature testing of Verilog parsers using fuzzing
- eigenform 2y agoReminds me that we're definitely overdue for replacing Verilog with something more deserving of the title "universal IR for EDA/hardware design tools" Can't help but feel like there's some kind of Conway's Law type-of-thing here: industry didn't evolve to be as "open" as software, so the interfaces are largely a function of the historical momentum of things.
- AgentOrange1234 2y agoWelp, this is going to be a miserable slog. I had the misfortune of writing a SystemVerilog parser once upon a time. The grammar is a huge and ambiguous muddle. SVA is a beast with no clear precedence on some of the operators. The standard's description of the preprocessor is an incoherent mess. Godspeed!