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I refused to buy the so determined defective chips even if they represented better value because if the intent was truly to try and max yield then there should

I refused to buy the so determined defective chips even if they represented better value because if the intent was truly to try and max yield then there should be for Ryzen for example good 7 core versions with only 1 core that was found to be defective. Since no 7 core zens exist, then at least some of the CPUs with 6 core CCDs have intentionally had 1 of the cores destroyed for reasons unknown, which could be to meet volume targets. If this is because for Ryzen the cores can only be disabled in pairs, then it boggles my mind that it would not be economic given the $ diff of tens to hundreds of dollars between the 6 and 8 core versions that is does not make sense to add the circuits to allow each core to be individually fused off and allow further product differentiation, especially considering how much effort and # of SKUs have been put forth with the frequency binning in AM4 (5700x, 5800, 5800x, 5800xt, etc.), rather than bigger market segmentation jumps.

AnthonyMouse 2y ago
> if the intent was truly to try and max yield then there should be for Ryzen for example good 7 core versions with only 1 core that was found to be defective. Since no 7 core zens exist There are Zen processors that use 7 cores per CCD, e.g. Epyc 7663, 7453, 9634. The difference between Ryzen and Epyc is the I/O die. The CCDs are the same so that's presumably where they go. Another reason you might not see this on the consumer chips is that they have higher base clocks. If you have a CCD where one core is bad and another isn't exactly bad but can't hit the same frequencies as the other six, it doesn't take a lot of difference before it makes more sense to turn off the slowest than lower the base clock for the whole processor. 6 x 4.7GHz is faster than 7 x 4.0GHz, much less 7 x 2.5GHz. In theory you could let that one core run at a significantly lower speed than the others, but there is a lot of naive software that will misbehave in that context. Whereas the base clock for the Epyc 9634 is 2.25GHz, because it has twelve 7-core CCDs so it's nearly 300W, and doesn't want to be nearly 1300W regardless of whether or not most of the cores could do >4GHz.
- downvotetruth 2y ago
  To correct the example for the Epyc line, models appears to exist with 1 through 8 cores available except for 5.
  - AnthonyMouse 2y ago
    The Epyc models with lower core counts per CCD probably don't exist because of yields though. The 73F3 has two cores per CCD, so with eight CCDs it only has 16 cores. The 7303 also has 16 cores but two CCDs, so all eight cores per CCD are active. The 73F3 costs more than five times as much. That's weird if the 73F3 is the dumping ground for broken dice. Not so weird when you consider that it has four times as much L3 cache and higher clock speeds. The extra cores in the 73F3 aren't necessarily bad, they're disabled so the others can have their L3 cache and so they can pick the two cores from each CCD that hit the highest clock speeds. Doing that is expensive, especially if the other cores aren't all bad, but then you get better performance per core. Which some people will pay a premium for, so they offer models like that even if yields are good and there aren't that many CCDs with that many bad cores. At which point your premise is invalid because processors are being sold with cores disabled for performance reasons rather than yield reasons.
    - downvotetruth 2y ago
      > they're disabled so the others can have their L3 cache and so they can pick the two cores from each CCD that hit the highest clock speeds what or where does that follow from? One can take a CCD with 2+ cores and pin a process to a set (of the fastest) cores based on profiling the cores and those 2+ cores could use the L3 cache as needed; disabling cores at the hardware level is the waste as if they were not disabled, then that would allow other processes to be able to benefit from more than 2 cores to run when desired. The latter point of disabling cores for "better [frequency] performance per core Which some people will pay a premium for" is dubious especially for the Epyc server line. If that were true, then there should at least be 4 core or fewer SKUs for desktop Ryzen variant where apps like games are more likely to benefit from the higher clock.
      - 2y ago
tverbeure 2y ago
That’s first sentence is a spectacular non-sequitur.
MobiusHorizons 2y ago
I would guess that there is a desire to not create too many product tiers. I believe 6 core parts are made from 2 3-core CCXs, (rather than 4 and 2) so only one core is disabled per ccx.
- cinnamonteal 2y ago
  Current Ryzen and EPYC processors have 8 core CCXs. The 6 core parts used to be as you described, but are now a single CCX. The Zen C dies have two CCXs, but they are still 8 core CCXs, and are always symmetrical in core count. The big exception is that the new Zen 5 Strix Point chip has a 4 core CCX for the non-C cores. I think the Zen 4 based Z1 has a similar setup but don't remember and couldn't quickly find the actual information to confirm.
  - wtallis 2y ago
    The Ryzen Z1 was a weird one: two Zen4 cores plus four Zen4c cores all in one cluster, sharing the same 16MB L3 cache.
- Symmetry 2y ago
  It would be sort of cool if they could do direct to consumer sales with every core going at whatever its maximum speed is or turned off if to disrupted. But that's not something you could do through existing distribution channels, everyone presumes a fairly limited number of SKUs.

AnthonyMouse 2y ago

> if the intent was truly to try and max yield then there should be for Ryzen for example good 7 core versions with only 1 core that was found to be defective. Since no 7 core zens exist There are Zen processors that use 7 cores per CCD, e.g. Epyc 7663, 7453, 9634. The difference between Ryzen and Epyc is the I/O die. The CCDs are the same so that's presumably where they go. Another reason you might not see this on the consumer chips is that they have higher base clocks. If you have a CCD where one core is bad and another isn't exactly bad but can't hit the same frequencies as the other six, it doesn't take a lot of difference before it makes more sense to turn off the slowest than lower the base clock for the whole processor. 6 x 4.7GHz is faster than 7 x 4.0GHz, much less 7 x 2.5GHz. In theory you could let that one core run at a significantly lower speed than the others, but there is a lot of naive software that will misbehave in that context. Whereas the base clock for the Epyc 9634 is 2.25GHz, because it has twelve 7-core CCDs so it's nearly 300W, and doesn't want to be nearly 1300W regardless of whether or not most of the cores could do >4GHz.

downvotetruth 2y ago
To correct the example for the Epyc line, models appears to exist with 1 through 8 cores available except for 5.
- AnthonyMouse 2y ago
  The Epyc models with lower core counts per CCD probably don't exist because of yields though. The 73F3 has two cores per CCD, so with eight CCDs it only has 16 cores. The 7303 also has 16 cores but two CCDs, so all eight cores per CCD are active. The 73F3 costs more than five times as much. That's weird if the 73F3 is the dumping ground for broken dice. Not so weird when you consider that it has four times as much L3 cache and higher clock speeds. The extra cores in the 73F3 aren't necessarily bad, they're disabled so the others can have their L3 cache and so they can pick the two cores from each CCD that hit the highest clock speeds. Doing that is expensive, especially if the other cores aren't all bad, but then you get better performance per core. Which some people will pay a premium for, so they offer models like that even if yields are good and there aren't that many CCDs with that many bad cores. At which point your premise is invalid because processors are being sold with cores disabled for performance reasons rather than yield reasons.
  - downvotetruth 2y ago
    > they're disabled so the others can have their L3 cache and so they can pick the two cores from each CCD that hit the highest clock speeds what or where does that follow from? One can take a CCD with 2+ cores and pin a process to a set (of the fastest) cores based on profiling the cores and those 2+ cores could use the L3 cache as needed; disabling cores at the hardware level is the waste as if they were not disabled, then that would allow other processes to be able to benefit from more than 2 cores to run when desired. The latter point of disabling cores for "better [frequency] performance per core Which some people will pay a premium for" is dubious especially for the Epyc server line. If that were true, then there should at least be 4 core or fewer SKUs for desktop Ryzen variant where apps like games are more likely to benefit from the higher clock.
    - 2y ago

tverbeure 2y ago

That’s first sentence is a spectacular non-sequitur.

MobiusHorizons 2y ago

I would guess that there is a desire to not create too many product tiers. I believe 6 core parts are made from 2 3-core CCXs, (rather than 4 and 2) so only one core is disabled per ccx.

cinnamonteal 2y ago
Current Ryzen and EPYC processors have 8 core CCXs. The 6 core parts used to be as you described, but are now a single CCX. The Zen C dies have two CCXs, but they are still 8 core CCXs, and are always symmetrical in core count. The big exception is that the new Zen 5 Strix Point chip has a 4 core CCX for the non-C cores. I think the Zen 4 based Z1 has a similar setup but don't remember and couldn't quickly find the actual information to confirm.
- wtallis 2y ago
  The Ryzen Z1 was a weird one: two Zen4 cores plus four Zen4c cores all in one cluster, sharing the same 16MB L3 cache.
Symmetry 2y ago
It would be sort of cool if they could do direct to consumer sales with every core going at whatever its maximum speed is or turned off if to disrupted. But that's not something you could do through existing distribution channels, everyone presumes a fairly limited number of SKUs.