I'd expect it to be MAC hardware embedded on the DRAM die (or in the case of stacked HBM, possibly on the substrate die). To quote from an old article about su

I'd expect it to be MAC hardware embedded on the DRAM die (or in the case of stacked HBM, possibly on the substrate die). To quote from an old article about such acceleration which sees 19x improvements over DRAM + GPU: Since MAC operations consume the dominant part of most ML workload runtime, we propose in-subarray multiplication coupled with intra-bank accumulation. The multiplication operation is performed by performing AND operations and addition in column-based fashion while only adding less than 1% area overhead. https://arxiv.org/pdf/2105.03736 https://arxiv.org/pdf/2105.03736