A decade ago, https://pycpu.wordpress.com/ https://pycpu.wordpress.com/ was a prototype that turned a small subset of Python bytecode, as well as the specificat

A decade ago, https://pycpu.wordpress.com/ https://pycpu.wordpress.com/ was a prototype that turned a small subset of Python bytecode, as well as the specifications for a system to run it, into VHDL/Verilog (via myhdl.org) to run on an FPGA. In theory, I imagine it would be possible to take this approach and transpile something like https://doc.pypy.org/en/latest/interpreter.html https://doc.pypy.org/en/latest/interpreter.html to an HDL. But a more reasonable thing to do would be to look down the road that JIT's and other similar technologies are coming to mainline CPython, see e.g. https://tonybaloney.github.io/posts/python-gets-a-jit.html https://tonybaloney.github.io/posts/python-gets-a-jit.html - and thus it might make sense to have some of the unique semantics of Python opcodes be adopted by specifications like ARM, similar to how ARM created the FJCVTZS opcode to exactly match Javascript's ToInt32 specification: https://stackoverflow.com/questions/50966676/why-do-arm-chips-have-an-instruction-with-javascript-in-the-name-fjcvtzs https://stackoverflow.com/questions/50966676/why-do-arm-chip... -> https://tc39.es/ecma262/#sec-toint32 https://tc39.es/ecma262/#sec-toint32