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Got me thinking, from what I've read, modern high-performance cores do a lot of similar tricks and translate everything to uops anyway. How hard would it be fo
by magicalhippo 2y ago
Got me thinking, from what I've read, modern high-performance cores do a lot of similar tricks and translate everything to uops anyway.
How hard would it be for say AMD to make a performant dual-ISA CPU?
I was thinking somewhat like how virtual 8086 mode[1] worked on 32bit CPUs, ie OS could be ARM-based, but it could run x86 processes.
I assume it would be hard to not sacrifice performance for one of the ISAs, but if it's for legacy applications you wouldn't need top speed necessarily.
Are ARM and x86 just too different to make it work? Are there other obstacles?
[1]: https://en.wikipedia.org/wiki/Virtual_8086_mode https://en.wikipedia.org/wiki/Virtual_8086_mode
- astrange 2y ago> Got me thinking, from what I've read, modern high-performance cores do a lot of similar tricks and translate everything to uops anyway. It's not really true. The uops are highly related to the input instructions. There's enough room in a big desktop CPU to fit a big complex decoder yes, but it's a waste of space you could be using for other things, namely even more caches. But the main reason not to do it is that you can do emulation or recompilation in software instead.