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I'm building a stained glass window for our front entrance, as a sometimes chip designer it's going to be a half adder (so much much smaller than a pentium) - t
by Taniwha 2y ago
I'm building a stained glass window for our front entrance, as a sometimes chip designer it's going to be a half adder (so much much smaller than a pentium) - the big challenge is showing all the layers (si, implantation, poly, metal, vias etc) I'm only doing 1 level of metal. The result is going to be more of a thin layered sculpture than a traditional stained glass window
- bankcust08385 2y agoNeat. 2 RTL gates -> 16 CMOS transistors (10 for XOR and 6 for OR)
- Taniwha 2y agoActually I misspoke, it's a full adder and very similar to the one on page 5 here https://www.cerc.utexas.edu/~jaa/vlsi/lectures/8-1.pdf https://www.cerc.utexas.edu/~jaa/vlsi/lectures/8-1.pdf
- anthonix1 2y agoDon't bother with the rectilinear pakeha layouts, do your half adders in curvilinear patterns, Koru style
- Taniwha 2y agoI am pakeha and tangata triti .... now I have an idea for the next window (I was thinking about a neuron ...)
- anthonix1 2y agoAHh gotcha. Well yeah I reckon you render a full custom 4004 w/ koru patterned transistors into about 4m x 4m stained glass panel. Would look good as the foyer panel for the CS dept at the University of Waikato
- kragen 2y agothis sounds awesome! do you have drawings?
- Taniwha 2y agoYes, I'm at the cut cartoon stage, just choosing glass it's a long thin panel so I needed a design of about the same shape - what I'm building (actually a full adder, I misspoke above) looks a lot like the design on page 5 here https://www.cerc.utexas.edu/~jaa/vlsi/lectures/8-1.pdf https://www.cerc.utexas.edu/~jaa/vlsi/lectures/8-1.pdf