Interesting read. It's quite intriguing that x86-64 processors of different microarchitectures and from different vendors basically all have similar non-determ

Interesting read. It's quite intriguing that x86-64 processors of different microarchitectures and from different vendors basically all have similar non-determinsm for retired instruction counters but — at least in the authors’ brief review — IA64 (Itanium), POWER, and SPARC appear to be too deterministic. I can't really see any good explanation for why this would be hard to get right specifically on x86-64. Can anyone else? (And are there any more recent or thorough results on other archs, particularly arm64?)