3 ms·
I'm interested in the collection of small cooperating chips on a common fabric approach. Essentially the chiplet work being done by AMD, which seems to have som
by JonChesterfield 2y ago
I'm interested in the collection of small cooperating chips on a common fabric approach. Essentially the chiplet work being done by AMD, which seems to have some options for third party silicon running on the same fabric.
I suspect, but do not know for sure, that verilog is going to emerge as the root cause for a wide variety of cost and error problems in silicon design. I'm therefore interested in non-verilog approaches to describing chips, but only at the casual / hobby level for now.
- mikewarot 2y agoIt seems that most chips are funneled through Verilog/RTL, and there aren't any ways to get around it for TinyTapeout. I'll keep looking, though.
- mikewarot 2y agoIt turns out that TinyTapeout doesn't gate the power to the digital submissions, so they need the GDS to be auto-generated to not take down the whole chip. If you want to route things yourself, I suppose you could use their new analog pin support, for which they gate power to keep the rest of the chip safe.