I know a bit of AMD GPU machine code, and it seems based on what I heard that RISC-V has only support for 'GPU vector' instructions, not 'GPU scalar' instructio

I know a bit of AMD GPU machine code, and it seems based on what I heard that RISC-V has only support for 'GPU vector' instructions, not 'GPU scalar' instructions, namely no "hardware thread mask" definition. And I heard that RISC-V GPU ISA was already extended with raytracing hardware instructions. For sure, 3D pipeline programing will be specific to one implementation, but since vulkan/dx12, it would have to be hardware command ring buffers (like for AMD GPUs).