3 ms·
> the top end of performance is not great I wonder how much is possible on that level. Not an expert myself, but I've read a critique on RISCV ISA by a ISA des
by sugarkjube 2y ago
> the top end of performance is not great
I wonder how much is possible on that level. Not an expert myself, but I've read a critique on RISCV ISA by a ISA designer [1] which I think mentioned several design choices that may make it more difficult optimize for performance (e.g. longer pipelines, issues with branch prediction), an easy to understand issue is explained in the introduction of that critique.
[1] https://news.ycombinator.com/item?id=24958423 https://news.ycombinator.com/item?id=24958423
- brucehoult 2y ago> critique on RISCV ISA by a ISA designer You mean an ex-Arm engineer. Of which Arm has thousands. And not an ISA designer or (more relevantly) CPU designer, but as the post itself says a verification engineer. Actual top high performance CPU designers, such as Jim Keller, say that RISC-V is just fine.