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It is not that Sufficiently Smart Compiler arrives or not. The problem is that VLIW architectures are a moving target - you can only really optimize for one spe
by garganzol 2y ago
It is not that Sufficiently Smart Compiler arrives or not. The problem is that VLIW architectures are a moving target - you can only really optimize for one specific chip. The next iteration of the same architecture brings a totally different superposition of performance considerations, thus rendering the previous optimization strategies inefficient.
This is the Achilles Heel of any VLIW architecture. A Sufficiently Smart Compiler gets outdated with a new chip revision. The previously compiled binary files that worked fast on a previous revision of the architecture, start to work slowly on newer chips.
- Y_Y 2y agoUnless the architecture is also an input. "Given the following C code, emit assembly for an architecture with the following characteristics." Why not? (Apart from the difficulty of writing a sufficiently general sufficiently smart compiler) I'm now imagining a world where Itanium took the place of RISC-V and we had a new generation of custom chips based on it.