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But if they do formal verification, then at least SV assertions should be present; will talke another look at the code.
by Rochus 2y ago
But if they do formal verification, then at least SV assertions should be present; will talke another look at the code.
- wren6991 2y agoYosys supports very basic SVA (immediate assert/assume, $past etc) in addition to Verilog 2005