3 ms·

At a guess it's because the author has been using Yosys for some formal verification work and maybe for doing some synthesis trials and it doesn't support syste

At a guess it's because the author has been using Yosys for some formal verification work and maybe for doing some synthesis trials and it doesn't support system verilog natively. Though things are improving there: https://github.com/chipsalliance/synlig https://github.com/chipsalliance/synlig

Rochus 2y ago
But if they do formal verification, then at least SV assertions should be present; will talke another look at the code.
- wren6991 2y ago
  Yosys supports very basic SVA (immediate assert/assume, $past etc) in addition to Verilog 2005