Huh, in what situation would vl=0 clobbering registers be undesirable while on vl≥1 it's fine? If hardware will be predicting vl, I'd imagine that would break

Huh, in what situation would vl=0 clobbering registers be undesirable while on vl≥1 it's fine? If hardware will be predicting vl, I'd imagine that would break down anyway. Potentially catastrophically so if hardware always chooses to predict vl=0 doesn't happen.