A basic exercise in mathematical logic involves looking for minimal sets of connectives. You can base logic on just NAND. But you get NOT by joining two inputs

A basic exercise in mathematical logic involves looking for minimal sets of connectives. You can base logic on just NAND. But you get NOT by joining two inputs together, so you might refuse to count that and say it is NOT and AND. Another possibility for binary logic is implication, =>, and NOT. Because (NOT A) => B is equivalent to A OR B and obviously (OR and NOT) work just as well as (AND and NOT). What though are minimal sets for ternary? The familiar 74181 has control inputs to let the circuit summon any of the 16 operations on two bits. (A two bit operation has four possible inputs, and two possible outputs for each input so 2 ^ 4 = 16 possible operations). A similar ALU part for ternary would have two trits as input so nine possible inputs. Each would have three possible values, so 3 ^ 9 = 19683. It would need nine control inputs, each a trit. But 19683 is so much more than 16. How many gates do you need to be able to combine them to produce all possible (trit,trit)->trit gates? Here are three gates that get you a long way mathematically. First a swap gate -1 -> 0 0 -> -1 1 -> 1 Then a permute gate -1 -> 0 0 -> 1 1 -> -1 This lets your generate all permutations Then you need a "spot" gate that spots one input, say (0 0) and output 1, and 0 otherwise. Since you have all permutations you have all spot gates. And inverse spot gates. Does that solve the problem? It is late and I'm tired. And I can see that the mathematically minimal set is impractical. https://commons.wikimedia.org/wiki/File:Balanced_ternary_operation_tables.svg https://commons.wikimedia.org/wiki/File:Balanced_ternary_ope... has six operations. There are three for doing arithmetic, the units from multiplication, the units from addition, and the carry from addition (it is part of the attraction of balanced ternary that there is no carry out from multiplying digits). There are also three for doing logic, based on -1 is false, +1 is true, and basically degenerating into binary logic. Is that how this is done? The Instruction Set Architecture (ISA) has two kinds of words, numbers in balanced ternary, and bit-rows in degenerate binary. The hardware is built with a pragmatic mixture of binary and ternary logic gates, with the ternary gates heavily used in the Arithmetic Unit, barely at all in the Logic unit, and only opportunistically in the rest of the hardware, that is mostly binary gates as usual? I have a bizarre mad science interest in this because I see how to build AND gates with mechanical linkages, http://alan.sdf-eu.org/linkage-logic/now-with-labels.html http://alan.sdf-eu.org/linkage-logic/now-with-labels.html and wonder if the same technique works for ternary gates. But what are the operation tables for ternary gates? I should attempt the specialized ones for arithmetic first.