3 ms·
Good point. Claim: Three-state logic can be advantageous in a digital system with a shared bus. The third state, Hi-Z, effectively disconnects a device from th
by xpe 2y ago
Good point.
Claim: Three-state logic can be advantageous in a digital system with a shared bus. The third state, Hi-Z, effectively disconnects a device from the bus. It allows multiple devices to share a single line efficiently.
Does the above claim overlook anything fundamental about where tristate logic shines?
There are alternative ways to design buses, but my EE-fu is not particularly current (pun intended). If others want to weigh in, please go ahead... e.g. open drain, multiplexing, TDMA, etc.
- dragontamer 2y agoI2C remains open collector today. The issue is that open collector is slow. It's hard to make a bus function above 1MHz and it won't go much beyond that. Sufficient for your typical temperature/ADC/whatever peripheral even today but 1Mhz is not very fast. 10kOhm pull-up will pull the bus back up to 3.3V or whatever your I2C operates at. Let's say each device on the bus adds 15pF of capacitance. At 6 devices, we are at 10kOhm * 6 * 15pF * 2.2 rise time == 2,000,000 ps rise time, aka 2us rise time aka 500kHz or somewhere in that neighborhood. (2.2 * RC constant gives the 80% rise time of a resistor-capacitor system. Capacitances in parallel add together. One 10kOhm pull-up resistor). ------- TriState buffers fix that by allowing a far greater drive of current into the bus. Current is the easiest way to fight back against fan-out * capacitance. Every chip will add parasitic capacitance and it actually adds up to real issues in practice.