Potentially (likely) uninformed question: Doesn't this have the potential side-effect of wrecking L1/L2 caches? If so that could get quite pathological for many

Potentially (likely) uninformed question: Doesn't this have the potential side-effect of wrecking L1/L2 caches? If so that could get quite pathological for many workloads. Or is there some new fancy dedicated hardware registers involved?