4 ms·

As a layman I don't understand this. Why would we sacrifice half the cores for an architecture choice on the same device? Why not provide 4 cores and settle on

As a layman I don't understand this. Why would we sacrifice half the cores for an architecture choice on the same device? Why not provide 4 cores and settle on an architecture? There must be something I don't understand or some strong use cases I'm not familiar with.

atoav 2y ago
Not that I am too familiar with the matter, but maybe the cores are not "real" independent cores, but share so much of the surrounding die that you have to make the choice. So it is not a quadcore where you can use only two, but a dualcore with an alternative architecture-part. In a different thread someone said that the part implementing the opcodes are really small, so doing both isn't that much of a tradeoff.
vardump 2y ago
If the cores share resources like ALU, routing, multiplier, etc. you can't run two cores that share same circuitry at same time. Edit: Correction: Eben Upton said the cores share no logic. https://news.ycombinator.com/item?id=41196880 https://news.ycombinator.com/item?id=41196880.
Taniwha 2y ago
My guess is it's essentially free to knock up a RISC-V core (there have been a couple in tiny tapeout) while ARM are getting aggressive and raising the price of their cores - by building a part than can run with 2 ARM cores or 2 RISCV cores RPi are thinking about their future, not only do they have a way to keep costs down if ARM tries to raise them simply by abandoning ARM but they also have a bargaining chip on the table when that negotiation happens There's going to be a pretty large number of code bases that when they get recompiled for RISC-V just work, that's going to be scary for ARM
- 15155 2y ago
  When packaged M0s run 6-8 cents, are they really getting "aggressive?" https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU-SOC_PUYA-PY32F002AL15S6TU_C5292060.html https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU...
  - snvzz 2y ago
    M0 are not comparable to M0+, which in turn are not comparable to M4 or M33. The RISC-V core in RP2350 is similarly performing to M33 except for the lack of FPU. Notably, SiFive's designs generally halve the area of similarly performing ARM ones, while being slightly faster and using significantly less power. ARM's become bloated.
    - 15155 2y ago
      https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU-SOC_PUYA-PY32F003W16S6TU_C5128437.html https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU... Here's an M0+ for an extra 4 cents - hopefully that won't break the bank. https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU-SOC_ARTERY-AT32F421F8P7_C2827821.html https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU... Or another 30 cents for an M4.
      - Narishma 2y ago
        They are using an M33 in the RP2350.
    - klelatti 2y ago
      > Notably, SiFive's designs generally halve the area of similarly performing ARM ones, while being slightly faster and using significantly less power. Source?
mkj 2y ago
The effort of interconnect to the rest of the chip isn't worth the tradeoff. https://news.ycombinator.com/item?id=41196841 https://news.ycombinator.com/item?id=41196841

atoav 2y ago

Not that I am too familiar with the matter, but maybe the cores are not "real" independent cores, but share so much of the surrounding die that you have to make the choice. So it is not a quadcore where you can use only two, but a dualcore with an alternative architecture-part. In a different thread someone said that the part implementing the opcodes are really small, so doing both isn't that much of a tradeoff.

vardump 2y ago

If the cores share resources like ALU, routing, multiplier, etc. you can't run two cores that share same circuitry at same time. Edit: Correction: Eben Upton said the cores share no logic. https://news.ycombinator.com/item?id=41196880 https://news.ycombinator.com/item?id=41196880.

Taniwha 2y ago

My guess is it's essentially free to knock up a RISC-V core (there have been a couple in tiny tapeout) while ARM are getting aggressive and raising the price of their cores - by building a part than can run with 2 ARM cores or 2 RISCV cores RPi are thinking about their future, not only do they have a way to keep costs down if ARM tries to raise them simply by abandoning ARM but they also have a bargaining chip on the table when that negotiation happens There's going to be a pretty large number of code bases that when they get recompiled for RISC-V just work, that's going to be scary for ARM

15155 2y ago
When packaged M0s run 6-8 cents, are they really getting "aggressive?" https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU-SOC_PUYA-PY32F002AL15S6TU_C5292060.html https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU...
- snvzz 2y ago
  M0 are not comparable to M0+, which in turn are not comparable to M4 or M33. The RISC-V core in RP2350 is similarly performing to M33 except for the lack of FPU. Notably, SiFive's designs generally halve the area of similarly performing ARM ones, while being slightly faster and using significantly less power. ARM's become bloated.
  - 15155 2y ago
    https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU-SOC_PUYA-PY32F003W16S6TU_C5128437.html https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU... Here's an M0+ for an extra 4 cents - hopefully that won't break the bank. https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU-SOC_ARTERY-AT32F421F8P7_C2827821.html https://www.lcsc.com/product-detail/Microcontrollers-MCU-MPU... Or another 30 cents for an M4.
    - Narishma 2y ago
      They are using an M33 in the RP2350.
  - klelatti 2y ago
    > Notably, SiFive's designs generally halve the area of similarly performing ARM ones, while being slightly faster and using significantly less power. Source?

mkj 2y ago

The effort of interconnect to the rest of the chip isn't worth the tradeoff. https://news.ycombinator.com/item?id=41196841 https://news.ycombinator.com/item?id=41196841