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But not 2+2? That seems too bad to have each architecture run code based on their strengths for quad core workloads.
by ravetcofx 2y ago
But not 2+2? That seems too bad to have each architecture run code based on their strengths for quad core workloads.
- simcop2387 2y agoYea, i was hoping for 2+2 myself but I suspect it's because the setup doesn't have the ability to mediate peripherals between the cores in a way that'd let that work. I.e. trying to turn on both Risc-v and arm #1 cores means that there'd be bus conflicts. It'd be cool if you could disable the io on the risc-v cores and do all hardware io through arm (or vice versa) so you can use the unconnected ones for just pure compute tasks (say run ws2812b led strips with the arm cores but run python/javascript/lua on the risc-v cores to generate frames to display without interrupting the hardware io).
- nine_k 2y agoWhy not both: power distribution and cooling? Having to route twice as many wide buses, and put in twice as much of L0 caches?
- ebenupton 2y agoWe did look at this, but the AHB A-phase cost of putting a true arbiter (rather than a static mux) on each fabric port was excessive. Also, there's a surprising amount of impact elsewhere in the system design (esp debug).