4 ms·

Compared to RP2040: Larger package (60 or 80 pins) Variant with 2 MB in-package Flash Secure boot and encrypted boot Two security execution contexts Random

Compared to RP2040: Larger package (60 or 80 pins) Variant with 2 MB in-package Flash Secure boot and encrypted boot Two security execution contexts Random number generator SHA-256 accelerator 8 kB of OTP ROM (separate from the 32 kB BOOTROM) 8 channel HSTX high speed serial transmitter 30->48 GPIO (18 more, in the 80 pins) 8->12 PIO state machines 12->16 DMA channels RISC-V and ARM (selectable at boot, individually per core) Cortex-M0+->Cortex-M33 (I don't know what that means in practice) 133->150 MHz core clock https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.p...

Narishma 2y ago
> Larger package (60 or 80 pins) I think the 60 pin version is the same size as RP2040.
- tommiegannert 2y ago
  It's a QFN56, but yeah, basically the same.
qwertox 2y ago
One of the nicest datasheets I've seen. Not in terms of the product specs (which are also really nice), but in terms of layout and content.
- disqard 2y ago
  Thanks for calling that out! Indeed, that is a well-written technical book that one could read cover-to-cover. It has a clear progression of topics, and all of the text is beautifully written: "Once secure boot is enabled, the bootrom verifies signatures of images from all supported media: flash, OTP, and images preloaded into SRAM via the UART and USB bootloaders. At this point you lose the ability to run unsigned images; during development you may find it more convenient to leave secure boot disabled. The next section describes the generation of signed images to run on a secure-boot-enabled device." "The chip-level reset subsystem shares a register address space with other power management subsystems in the always-on domain. The address space is referred to as POWMAN elsewhere in this document. A complete list of POWMAN registers is provided in Section 6.4, “Power Management (POWMAN) Registers”, but information on registers associated with the brownout detector are repeated here." "The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock sources, allowing the user to trade off performance against cost, board area and power consumption. From these sources it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies." I am thoroughly impressed!!

Narishma 2y ago

> Larger package (60 or 80 pins) I think the 60 pin version is the same size as RP2040.

tommiegannert 2y ago
It's a QFN56, but yeah, basically the same.

qwertox 2y ago

One of the nicest datasheets I've seen. Not in terms of the product specs (which are also really nice), but in terms of layout and content.

disqard 2y ago
Thanks for calling that out! Indeed, that is a well-written technical book that one could read cover-to-cover. It has a clear progression of topics, and all of the text is beautifully written: "Once secure boot is enabled, the bootrom verifies signatures of images from all supported media: flash, OTP, and images preloaded into SRAM via the UART and USB bootloaders. At this point you lose the ability to run unsigned images; during development you may find it more convenient to leave secure boot disabled. The next section describes the generation of signed images to run on a secure-boot-enabled device." "The chip-level reset subsystem shares a register address space with other power management subsystems in the always-on domain. The address space is referred to as POWMAN elsewhere in this document. A complete list of POWMAN registers is provided in Section 6.4, “Power Management (POWMAN) Registers”, but information on registers associated with the brownout detector are repeated here." "The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock sources, allowing the user to trade off performance against cost, board area and power consumption. From these sources it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies." I am thoroughly impressed!!