3 ms·
They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions f
by swetland 2y ago
They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions from both cores.
- coder543 2y agoAll of the public mentions of this feature that I've seen indicated it is an either/or scenario, except the datasheet confirms what you're saying: > The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1. Practical applications for this are limited, since this requires two separate program images. That is fascinating... so, likely what dmitrygr said about the size of the crossbar sounds right to me: https://news.ycombinator.com/item?id=41192580 https://news.ycombinator.com/item?id=41192580
- moffkalast 2y agoDid Dr. Frankenstein design this SoC? Igor, fetch me the cores!
- ebenupton 2y agoIt's aliiiiiive!
- geerlingguy 2y agoIt was also confirmed by Eben Upton in an interview in The Register[1], and I believe Adafruit's livestream also mentioned it. [1] https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/ https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/