3 ms·

Coordinating access to the memory bus and peripherals is probably not easy to do when the cores weren’t ever designed to work together. Doing so could require a

Coordinating access to the memory bus and peripherals is probably not easy to do when the cores weren’t ever designed to work together. Doing so could require a power/performance penalty at all times, even though most users are unlikely to want to deal with two completely different architectures across four cores on one microcontroller. Having both architectures available is a cool touch. I believe I criticized the original RP2040 for not being bold enough to go RISC-V, but now they’re offering users the choice. I’ll be very curious to see how the two cores compare… I suspect the ARM cores will probably be noticeably better in this case.

swetland 2y ago
They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions from both cores.
- coder543 2y ago
  All of the public mentions of this feature that I've seen indicated it is an either/or scenario, except the datasheet confirms what you're saying: > The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1. Practical applications for this are limited, since this requires two separate program images. That is fascinating... so, likely what dmitrygr said about the size of the crossbar sounds right to me: https://news.ycombinator.com/item?id=41192580 https://news.ycombinator.com/item?id=41192580
  - moffkalast 2y ago
    Did Dr. Frankenstein design this SoC? Igor, fetch me the cores!
    - ebenupton 2y ago
      It's aliiiiiive!
  - geerlingguy 2y ago
    It was also confirmed by Eben Upton in an interview in The Register[1], and I believe Adafruit's livestream also mentioned it. [1] https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/ https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/

swetland 2y ago

They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions from both cores.

coder543 2y ago
All of the public mentions of this feature that I've seen indicated it is an either/or scenario, except the datasheet confirms what you're saying: > The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1. Practical applications for this are limited, since this requires two separate program images. That is fascinating... so, likely what dmitrygr said about the size of the crossbar sounds right to me: https://news.ycombinator.com/item?id=41192580 https://news.ycombinator.com/item?id=41192580
- moffkalast 2y ago
  Did Dr. Frankenstein design this SoC? Igor, fetch me the cores!
  - ebenupton 2y ago
    It's aliiiiiive!
- geerlingguy 2y ago
  It was also confirmed by Eben Upton in an interview in The Register[1], and I believe Adafruit's livestream also mentioned it. [1] https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/ https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/