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SERV – The SErial RISC-V CPU

• peter_d_sherman 2y ago
  ">the award-winning SERV is [possibly!] the world's smallest RISC-V CPU. It's the perfect companion whenever you need a bit of computation and silicon real estate is at a premium. How small is it then? Synthesizing the latest version of SERV in its most minimal form, yields the following results for some popular FPGA architectures and a typical CMOS process. Lattice iCE40 - 198 LUT, 164 FF Intel Cyclone 10LP - 239 LUT, 164 FF AMD Artix-7 - 125 LUT, 164 FF CMOS - 2.1kGE" Related: ASIC roundup of open source RISC-V CPU cores: https://bitlog.it/20220118_asic_roundup_of_open_source_riscv_cpu_cores.html https://bitlog.it/20220118_asic_roundup_of_open_source_riscv... >"SERV (RV32I, RV32IM, RV32Zicsr) The award-winning SERV CPU by Olof Kindgren is a bit-serial RISC-V CPU that is focussed on being as minimal as possible." Maximum clock frequency: 1020 MHz (1.02 Ghz) (<-Fastest clock speed of all compared Open Source/Open Hardware RISC-V CPU's in this article...) Die area: 0.029584 mm^2 Utilization rate: 78.868%"
  • snvzz 2y ago
    As an added note, the only slightly bigger QERV provides a huge performance bump.