4 ms·
I wonder whether any other ISAs support something similar. In 32 bit ARM you could get close with variations on a load/store instruction with an offset of 0.
by mmaniac 2y ago
I wonder whether any other ISAs support something similar.
In 32 bit ARM you could get close with variations on a load/store instruction with an offset of 0.
LDR R0, [R1]
LDR R0, [R1, #-0]
LDR R0, [R1, #0]!
LDR R0, [R1], #0
Same instruction but different addressing modes and therefore different mnemonics.
- 082349872349872 2y agoEven in the unlikely event an ISA were to have no semantic confusion possibilities, there are plenty of covert channels in binaries, eg rearranging runtime addresses. (then there's the binary itself: even if we were to restrict ourselves to loading exactly the same process image, in general there are many different executable files that would do so)
- phire 2y agoOr even just changing the order of instructions whenever there are no dependencies.