(I also agree with most things, and don't reply to those parts) > In the real world a lot of work was done to minimize that over x86’s lifetime. In the early

(I also agree with most things, and don't reply to those parts) > In the real world a lot of work was done to minimize that over x86’s lifetime. In the early days RISC did do a lot of what was promised, but clever (some would say hacky in some situations) updates to x86 CPUs and compilers made these advantages less (although one could argue the x86 microarchitectures that showed up in the mid to late 1990s were more RISC like). They were identical to RISC architectures, with the exception of a more complex decode unit, which led to extra transistors burning extra power and costing speed in the early Pentium days. That mattered a lot when a 1993 Pentium had 3.1 million transistors. That matters a lot less when a modern Intel CPU has ≈5 billion transistors. Fundamentally, that's what allowed x86 to pass all the various RISC architectures in speed. Those kinds of differences in instruction set just don't matter anymore. At that point, it was just R&D dollars, which Intel had more of due to volume. As a footnote: It's worth remembering StrongARM. The SA-110 was just as fast as the fastest Intel had to offer, when introduced in 1995, at a much lower price and power budget. It was crazy I could get a little embedded board for $100-$300 which was just as fast as $5000 computers. Intel acquired it from DEC. Oddly enough, it barely improved from there on. A decade later, clock speed went up 4x on the XScale (and only on the very top-end), and more than 15x on the x86.