The first comes with a lot of trade-offs, but I would love to see two QSPI controllers or at least two chip select lines that can be controlled by an extra addr

The first comes with a lot of trade-offs, but I would love to see two QSPI controllers or at least two chip select lines that can be controlled by an extra address bit. I also want the DMA engine to be able to address the SIO block to access the GPIOs and interpolators without having to "tunnel" through a different peripheral like PIO or PWM timers.