I definitely think it is worth exploring other models than the traditional randomly accessed register file. Your idea reminded me a bit of Scheduled Dataflow [

I definitely think it is worth exploring other models than the traditional randomly accessed register file. Your idea reminded me a bit of Scheduled Dataflow [0] architecture where every register is a dedicated input to a unit. Instead of an instruction having source and destination register parameters there are only destination registers. The Mill does it the other way around: There are only source operands and the result is stored in each unit's dedicated output register. [0]. https://www.semanticscholar.org/paper/Scheduled-Dataflow%3A-Execution-Paradigm%2C-and-Kavi-Giorgi/1250388ecf7d51ed97fb5da7b51af64c45553f8f https://www.semanticscholar.org/paper/Scheduled-Dataflow%3A-...