I understand how adding delays at every step seems like a really bad idea, especially when coming from a world of FPGAs and trying to squeeze out every nanoseco

I understand how adding delays at every step seems like a really bad idea, especially when coming from a world of FPGAs and trying to squeeze out every nanosecond of latency. What you get in trade, is an architecture that doesn't have any fiddly timing issues. You also get something that is inherently pipelined. So, in theory, you could shove data in one side of the fabric at the full clock rate, and get results out the other side at that same rate. I assume that it should be feasible to run a BitGrid at 1 Ghz, which means that if it's big enough, you could run real time FFTs, signal processing, etc... sure the latency sucks, but the throughput is enormous. I understand that wasting gates, instead of having dedicated routing hardware also seems like a horrible idea. What you get in trade, is freedom from the routing issues that always arise when you have a lumpy fabric with special functions in fixed locations. In theory (as all I have right now is theory), it should be trivial to move a whole section of the flow graph over 1 cell, or rotate, flip the flow, etc. Routing around a bad cell is going to incur a small penalty, perhaps as low as 1 full clock cycle in most cases. --- Do those trade-offs make sense? Maybe... or not.